Accumulator read port arbitration logic
US6175912A · kind A · utility
6Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1997 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Nov 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor architecture having an accumulator register file with multiple shared read and/or write ports. Depending on the instruction, each port can be used to communicate with a different data source or destination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.