Error correction apparatus and associated method utilizing parellel processing
US6175941A · kind A · utility
28Cited by
13References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1998 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Dec 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus, and an associated method, for performing error-correction operations to correct errors in a block of block-encoded data. Two ALUs are operable in parallel to perform finite-field mathematical operations and to calculate addresses used pursuant to the error-correction calculations. Instructions pursuant to which the ALUs are operable are stored in a memory device. The instructions are retrieved during operation of error-correcting calculations. The manner by which the error-correcting apparatus operates is alterable by appropriate alteration of the instructions stored at the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.