Arrangement for DRAM cell using shallow trench isolation
US6177697A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2000 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Jan 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/37
Abstract
A semiconductor structure uses a shallow trench isolation (STI) region to realize a capacitor trench of a reduced size. Consistent with one embodiment of fabricating a memory cell, the invention includes selectively removing portions of a substrate using a patterned mask to form a capacitor trench and an isolation trench at least partially around the capacitor trench. An oxide is formed in the isolation trench and the capacitor trench, and the oxide is selectively removed in the capacitor trench. Portions of the substrate defining the base and sidewalls of the capacitor trench are then doped and a capacitor dielectric is formed in the capacitor trench, leaving a portion of the trench unfilled. A polysilicon layer is formed it the unfilled portion of the capacitor trench and over the capacitor dielectric to form a plate of the storage capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.