Phase-locked loop or delay-locked loop circuitry for programmable logic devices
US6177844A · kind A · utility
41Cited by
27References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Sep 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0997
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device is provided with phase-locked loop ("PLL") or delay-locked loop ("DLL") circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides aL substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.