Power-electronic circuit arrangement for compensating for mains system disturbances and mains voltage reductions
US6178076A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Apr 2, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E40/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In a power-electronic circuit arrangement for compensating for mains system voltage reductions and mains system disturbances, a second auxiliary voltage source is provided, whose voltage is chosen to be less than that of the first auxiliary voltage source. The second auxiliary voltage source can be coupled to the feeder converter with the aid of a switch. The circuit according to the invention can thus operate in two different modes: when the first auxiliary voltage source is coupled to the feeder converter, the available voltage is sufficiently high to compensate for mains system failures or mains system voltage reductions. However, when less severe disturbances occur, the second, lower auxiliary voltage source is coupled to the feeder converter, and mains system disturbances can in consequence be compensated for without any major switching losses. The circuit then operates in a regulated mode, and the switching losses of the semiconductor switches in the feeder converter can be kept at an acceptable level, which is typically less than the losses when switched on. A further option for influencing the voltage is achieved by pulsing, in particular by pulse-width modulation of the sw…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.