Fractional decimator with linear interpolation and method thereof
US6178186A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0685
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to the present disclosure, an parallel formatted data signal is applied to an input (300), and the data signal is divided into a first data signal and a second data signal. The second data signal is applied to a logic delay element (606) to produce a delayed second data signal that is a delayed-in-time version of the first data signal. The first data signal is applied to a first parallel-to-serial converter (706), the delayed second signal is applied to a second parallel-to-serial converter (708), and first and second bit-serial data streams are produced. A controller (710) synchronizes an Arithmetic Logic Unit (616) to the first and second bit-serial data streams so that the ALU (616) scales and sums the first and second bit-serial data streams to produce a bit-serial, sample-rate converted, output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.