Multi-layer semiconductor devices with stress-relief profiles
US6178189A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | May 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/3201
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Multi-layer, semiconductor devices are configured to reduce stress by the removal of much of the structure which does not actually contribute to device performance. In one embodiment, trough between mesas which define light emitting facets in a laser diode bar are etched well into the substrate to remove all layers of different compositions there. In another embodiment, troughs are also etched in the backside of the substrate of a laser diode structure where the troughs are aligned along axes perpendicular to the axes of the mesas. The removal of stress permits more accurate alignment of the multiple facets along a single axis when the laser bar is bonded to a heat sink. The accurate alignment minimizes the placement constraints on the position of a microlens for achieving maximum power output and coupling efficiency for optical fibers coupled to the microlens.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.