PLD/ASIC hybrid integrated circuit
US6178541A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1998 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Mar 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprised of a customized circuit portion and a programmable logic portion that is interfaced to the customized circuit. The custom circuit and the programmable circuit are fabricated on a common semiconductor substrate to achieve maximum cost savings and performance advantages over implementations in which an external PLD or other programmable device is interfaced to a custom circuit. Suitably, the customized circuit is designed with an ASIC design flow to optimize the performance, power consumption, and size of the customized circuit. In the presently preferred embodiment, the programmable circuit comprises a plurality of programmable logic cells suitably generated by, in one embodiment, a PLD compiler. Ideally, the relative size and placement of said PLD with respect to said customized circuit are selectable during a design phase of said integrated circuit. This provides flexibility in determining how much of an interim device need be devoted to programmable circuitry. Presumably, during earlier stages of the design process, a larger percentage of the device will be devoted to the programmable portion. As the product definition matures, subsequent interim d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.