Reduced voltage input/reduced voltage output tri-state buffers
US6181165A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 9, 1998 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Mar 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed a tri-state buffer circuit for receiving an input signal at a buffer input node and transmitting, responsive to a buffer enable signal, an output signal at a buffer output node. The buffer circuit includes an input stage coupled to the buffer input node. The input stage is configured to receive, when the buffer enable signal is enabled, the input signal. The buffer circuit further includes a level shifter stage coupled to the input stage. The level shifter stage is arranged to output, when the buffer enable signal is enabled, a set of level shifter stage control signals responsive to the input signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the input signal. The buffer circuit also includes an output stage coupled to the level shifter stage. The output stage is configured to output, when the buffer enable signal is enabled, the output signal on the buffer output node responsive to the set of level shifter stage control signals. The voltage range of the output signal is lower than the voltage range of the set of level shifter stage control signals. The output stage decouples the buffer output…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.