High-speed rail-to-rail comparator
US6181169A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed rail-to-rail comparator is described. The comparator has two PMOS transistors, two NMOS transistors, a current source and two voltage-dropped components. A first PMOS transistor has a source terminal coupled to a first voltage source and a gate terminal and a drain terminal coupled to each other. A second PMOS transistor has a source terminal coupled to the first voltage source, and a gate terminal of the second PMOS transistor coupled to the gate terminal of the first PMOS transistor. A first NMOS transistor has a drain terminal coupled to the drain terminal of the first PMOS transistor and a gate terminal coupled to a reference signal. A second NMOS transistor has a drain terminal of the first NMOS transistor coupled to the drain terminal of the second PMOS transistor and coupled to an output terminal. A gate terminal of the second NMOS transistor is coupled to an input terminal and a source terminal of the second NMOS transistor is coupled to a source terminal of the first NMOS transistor. A first voltage-dropped component has a positive terminal coupled to the gate terminal of the second PMOS transistor and a negative terminal coupled to the drain terminal of the s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.