Clock generator and synchronizing method
US6181175A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Jun 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Network elements of a synchronous digital communications system have a clock generator for generating a clock signal locked to an input signal. Such a clock generator comprises a tunable oscillator (OSC) and a phase comparator (PK) for comparing the phase of the input signal (IN) with the phase of the clock signal (CLK) and for generating a correction signal which serves to tune the oscillator (OSC). To avoid phase transients due to interruptions and disturbances in the input signal (IN), means (WD) are provided for determining an expectancy window, for deciding whether the correction signal lies within the expectancy window, and for tuning the oscillator with the correction signal if the correction signal lies within the expectancy window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.