Flip-flop circuit
US6181180A · kind A · utility
19Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power, high performance flip-flop includes a first branch having a number of transistors connected in series, and a second branch having a number of transistors connected in series. A clock signal and a data input signal are coupleable to the first and second branches of the circuit, the circuit generating a stable logic one or logic zero. The circuit has low power consumption and high performance speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.