Low mismatch complementary clock generator
US6181185A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Jul 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Two complementary clocks that are well matched are produced from a single input clock. A clock buffer includes an alternating series of edge-rate-controlled inverters and level restoring inverters. The output of this series of inverters is compared to the input clock by a race timer. If the output of the series of inverters switches in the opposite direction before the input clock, the edge rates of the series of inverters are slowed down. If the output of the series of inverters switches in the opposite direction after the input clock, the edge rates of the series of inverters are speeded up. The output of the series of inverters eventually approaches the timing of the input clock but complemented. These signals form a pair of complementary clocks with well matched timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.