VCXO with reduced PWM effects high slew rate conditions
US6181217A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Jul 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B5/368
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A VCXO having reduced PWM effects includes an inverter (U1) having a DC feedback path (Rf) for biasing the inverter to a linear operating range and having an AC feedback path (40) for causing oscillations to occur and for varying the frequency of said oscillations in accordance with a frequency control bias voltage, Vbias. The AC feedback path includes a tank circuit (28) comprising a crystal (X1) having a first plate (22) coupled to an output (2) of the inverter via a source resistance (Rx), coupled to a source of reference potential via a varactor diode (D1) and coupled to a source (R1,T2) of the bias voltage (Vbias). The crystal (X1) has a second plate (24) coupled to an input of the inverter and coupled to the source of reference potential via a capacitor (C2) of fixed value. The source resistance is of a relatively high value selected to substantially attenuate the bias voltage whereby both the input and the output terminals of the inverter are effectively isolated from the bias voltage source. Advantageously, the PWM effect is reduced, the tuning range is extended and crystal power dissipation is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.