Graphics pipeline selectively providing multiple pixels or multiple textures

US6181352A · kind A · utility

Assignee

• NVIDIA Corporation · US

Inventors

• David B. Kirk · Telluride, US
• Gopal Solanki · San Jose, US
• Curtis Priem · Fremont, US
• Walter E. Donovan · Saratoga, US
• Joe L. Yeun · San Jose, US

Key dates

• Filing date: Mar 22, 1999
• Grant date: Jan 30, 2001
• Expiry date: Mar 22, 2019

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/005
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A graphics accelerator pipeline including a combiner stage capable of producing output values during each clock interval of the pipeline which map a plurality of textures to a single pixel or an individual texture to two pixels.