Semiconductor package substrate and semiconductor package
US6181560A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Oct 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A component for forming a chip package includes a flat insulative plate. A heat sink is embedded in a central portion of the plate, and a plurality of electrically conductive leads are embedded in peripheral portions of the insulative plate. The leads extend from the top surface of the plate to the bottom surface of the plate, and may also be exposed on side edges of the plate. A recess for receiving a chip may be formed at a central portion of the plate. A chip package utilizing the plate would include a chip mounted on the heat sink, a plurality of wires or solder bumps that connect bond pads on the chip to corresponding leads in the plate, and an insulating material that covers the chip. The insulating material could be a molding resin, or a separate cover plate that covers the chip. In the case of a cover plate, the cover plate may also include an embedded heat sink and embedded leads that can be connected to the embedded leads of the insulative plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.