Dynamic type RAM
US6181618A · kind A · utility
14Cited by
6References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1998 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Mar 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is to provide a semiconductor memory device capable of realizing a high speed sensing operation and an enlarged sense margin, for ensuring the sensing operation even with a low power source voltage by connecting the bit line of the memory cell array portion and the bit line of the sense amplifier portion via the P-type transfer gate, having the bit line amplitude of the sense amplifier potion larger than the bit line amplitude of the memory cell array portion, and having different precharge voltages for the bit line of the sense amplifier portion and the bit line of the memory cell array portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.