Semiconductor memory device with a reduce access time by devising a layout of a circuit without elaborate modification
US6181631A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Apr 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is an object of the invention to provide a semiconductor memory device with a reduced access time by devising a layout of a circuit without elaborate modification. A Y address buffer is situated on the side of an address pad array (the right side), and outputs a signal for controlling Y address decoder situated on the right side and a circuit block communicated therewith. The Y address decoders on the right side control the Y addresses of memory cells in the memory cell arrays C and D in case that data are read therefrom or written thereinto. The circuit block communicated with the Y address buffer outputs a signal to the address decoders on the side of a DQ pad array (the left side) in accordance with the signal inputted from the Y address buffer. The Y address decoders on the left side control the Y addresses of the memory cells in the memory cell arrays A and B in accordance with the signal inputted from the circuit block communicated with the Y address buffer. Data amplifiers combined with the memory cell arrays A, B, C and d respectively amplify the data read from the memory cells in the memory cell arrays A, B, C and D. The circuit blocks situated on both the side ends of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.