Memory device having reduced power requirements and associated methods
US6181641A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | May 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory cells arranged in rows and columns. The memory cells are divided into a plurality of sub-arrays. The memory cell further includes a plurality of word lines connecting rows of the memory cells, and a plurality of bit line pairs connecting columns of the memory cells. An address transition detect (ATD) circuit detects an address transition for a selected memory cell and generates an ATD pulse in response thereto. A respective bit line precharge circuit is associated with each of the plurality of sub-arrays. An ATD pulse distribution circuit distributes the ATD pulse to only a selected sub-array containing the selected memory cell to activate only the bit line precharge circuit of the selected sub-array and not activate precharge circuits of other non-selected sub-arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.