Digital matched filter
US6181733A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 19, 1998 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Nov 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0254
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Consumption power is reduced in a digital matched filter for determining a correlation value between a digital signal (I.sub.o) of 6 bits, which is synchronous with a clock, and a despreading code sequence (C.sub.7 C.sub.6 C.sub.5 C.sub.4 C.sub.3 C.sub.2 C.sub.1 C.sub.0) which includes 8 despreading codes. First to eighth flip-flop sets (211-218) constituting a storage section (210) are sequentially selected clock by clock by a write selection circuit (220), and the digital signal (I.sub.o) is stored in the selected flip-flop set. The 8 despreading codes are stored in first to eighth code flip-flops (231-238), respectively, and are shifted in synchronism with the clock. Output signals of the first to eighth flip-flop sets are multiplied by output signals of the first to eighth code flip-flops in first to eighth multiplication circuits (241-248), respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.