Receiver synchronisation in idle mode
US6181755A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 20, 1997 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | May 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver is synchronised to a signal by studying which among the previously calculated responses to known synchronisation errors corresponds to the response of a real, received signal. A sample sequence decimated from an oversampled signal is compared to model sequences which correspond to decimation at a different distance from the optimum decimation point, and in further processing the employed decimation point is used according to how far from optimum the best correlated model sequence is situated. From the phase angles of the samples, there is calculated an average phase angle change per symbol, and on the basis of that and the known symbol rate, the frequency error in the reception is determined. For each sample of the data burst, there is calculated an individual phase correction by multiplying the individually defined average phase shift per symbol by the distance from a given symbol corresponding to a phase reference value, and by adding the result to said phase reference value. Bursts are received in groups, and timing and frequency errors are predicted on the basis of the trends indicated by preceding groups in order to receive the next group. A unit formed of several g…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.