Method and tool for computer bus fault isolation and recovery design verification
US6182248A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1998 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Apr 7, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error injection tool, connected to a bus to be tested in such a manner as not to interfere with normal operation, is employed for error detection and recovery design verification. The error injection tool is connected to the bus to be tested within a data processing system, the system is powered on, and applications simulating normal system loading are run. A desired error is then selected, and the error injection tool is actuated. The error injection tool monitors bus cycles and transactions through selected signals and, upon detecting an appropriate cycle or transaction, overdrives a selected conductor within the bus being tested to inject an error. The selected bus conductor is overdriven (forced) to a logic high or a logic low for a single clock cycle, simulating the intermittent nature of errors likely to occur during normal operation. Bus error signals are then monitored to ascertain whether the error was successfully injected. If not, subsequent attempts during appropriate bus cycles or transaction may continue until error injection is successful. Once an error is successfully injected, the operation of fault isolation and recovery facilities for the bus being tested may …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.