Method of forming integrated circuit capacitors having electrodes therein that comprise conductive plugs
US6184551A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Oct 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/696
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a capacitor of semiconductor integrated circuit and a method for fabricating the same by which characteristic of a capacitor and bit resolution can be improved to thereby obtain an improved analogue device of high accuracy. The capacitor of semiconductor integrated circuit includes a conductive lower electrode formed on a predetermined portion of an insulating substrate, an insulating layer formed on the insulating substrate including the conductive lower electrode and provided with a via hole so that the surface of the lower electrode is exposed in its predetermined portion, a dielectric layer formed on the insulating layer and in the via hole, and an conductive upper electrode formed on the predetermined portion of the dielectric layer including the via hole to have a piled structure such as "conductive plug/conductive layer pattern".
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.