Integrated circuit dies including thermal stress reducing grooves and microelectronic packages utilizing the same
US6184570A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an integrated circuit die having first and second opposing faces, a plurality of spaced apart bonding regions on the first face, and at least one groove in the second face. The at least one groove allows the die to flex upon application of stress to the bonding regions due to thermal cycling of the integrated circuit die, compared to absence of the at least one groove. Preferably, multiple grooves are provided, a respective one of which extends between a respective pair of adjacent spaced apart bonding regions. The grooves may be fabricated by sawing and/or etching the grooves in the second face. The sawing and/or etching may be performed at the wafer stage, before the integrated circuit dies are singulated. Alternatively, the sawing and/or etching may take place after the integrated circuit dies are singulated from the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.