Design method for compensation of process variation in CMOS digital input circuits
US6184704A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1999 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Feb 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention describes an improved design of CMOS. digital input circuits. This improvement reduces the switching level uncertainty range and thus increases the noise margin, compensating for manufacturing process variations. This improvement is achieved by providing resistive compensation devices in series with the P-type and the N-type CMOS transistors in the first stage of a multistage digital input circuit. These resistive devices can be implemented by means of resistors or by means of MOSFET devices which provide the required resistive function. These compensation devices modify the input-output voltage transfer characteristics of the first stage so as to reduce the switching level variation at the input to the circuit. The resulting digital input circuit has a greater tolerance to input noise levels. The improvement provided by this invention is particularly important as integrated circuits design trend is to operate with lower supply voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.