Digital phase locked loop
US6184734A · kind A · utility
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3References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 17, 1999 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | May 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase locked loop is provided that includes a phase comparator for receiving an incoming signal with which is desired to lock. A loop filter processes a current error signal. An integrator adjusts the output to account for the error. The phase comparator, loop filter and integrator are formed from logic elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.