Robust wordline activation delay monitor using a plurality of sample wordlines
US6185135A · kind A · utility
5Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1999 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Jan 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wordline activation delay monitor circuit is disclosed wherein at least one sample wordline and a sample wordline redundancy are located within the same data-storing array region of a memory, and a sample wordline selector is coupled to activate the sample wordline or sample wordline redundancy based on the state of a nonvolatile input. The wordline selector circuit may include one or both of a row decoder circuit or a wordline driver circuit which have substantially the same structure and location as row decoder circuits and wordline driver circuits used to activate wordlines within the data-storing array region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.