ATM cell processing apparatus
US6185212A · kind A · utility
17Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Apr 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An ATM cell processing apparatus including a DRAM for a frame producing buffer of a frame producing unit. In order to absorb the anisotropy of the access rate of the DRAM access, the random access mode of the DRAM access is always used. To compensate a drop in access rate in this case, the DRAM is arranged is an array form and each cell is divided. Resultant partial cell data are written into and read from respective DRAM banks in order. As a result, a fast cell buffer having a large capacity can be formed. The present cell buffer can be applied to a FIFO and the like as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.