DMA configurable receive channel with memory width N and with steering logic compressing N multiplexors
US6185633A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Mar 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A descriptor controlled transmit and receive scatter/gather Direct Memory Access Controller efficiently moves data frames comprised of scattered blocks of data from within memory to a destination interface via a multibyte-wide buffer. The transfer of frames into a transmit buffer and out of a receive buffer is optimized regardless of the total length of the component data blocks and regardless of whether the data blocks include an odd or even number of bytes, whether the data blocks begin at an odd or even address, or whether the data blocks are misaligned with regard to memory width boundaries. A DMAC in accordance with an embodiment of the present invention stores information provided by a descriptor before frame processing takes place. This information in conjunction with steering logic and accumulator registers is used to control the steering and storing of the frame data as it passes through the DMAC to the transmit buffer or from the receive buffer. An alternate embodiment of the present invention performs these functions based on the present values of the descriptor fields. Using predetermined data block descriptor information, the present invention is able to determine on t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.