Minimal frame buffer manager allowing simultaneous read/write access by alternately filling and emptying a first and second buffer one packet at a time
US6185640A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 19, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Jun 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/10527
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and arrangements are provided for a block decoder in the form of a single integrated circuit (IC) for use in a variety of data storage devices. The block decoder is configured to transfer streaming data from the storage medium to an external device, such as a host computer's processor, without introducing any significant overhead induced latency into the data transfer. This is accomplished by employing a purely hardware-based logic and substantially minimizing the amount of buffering of data that is required within the storage device. The resulting block decoder can be integrated into a single IC because the amount of buffering memory that is required can be economically fabricated using conventional logic fabrication processes, such as complementary metal oxide semiconductor (CMOS) processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.