Interrupt mechanism on NorthBay
US6185652A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Nov 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt tracking mechanism includes a CPU that handles interrupts generated by an interrupt generator, a storage element accessible to the CPU, an interrupt counter implemented in hardware and a single set of interrupt status-registers. The interrupts are generated by the interrupt generator in an order determined by the order of tasks sent by the CPU to the interrupt generator and indicate completion of those tasks. The CPU can maintain in the storage element an ordered list of at least a contiguous subset of the tasks sent to the interrupt generator. The CPU can also maintain in the storage element a count of tasks sent to the interrupt generator as part of the contiguous subset. For each interrupt it generates the interrupt generator increments the count in the interrupt counter and writes the address of the interrupt to the interrupt status register. Because a single interrupt status register is used, only the status information for the latest interrupt is available in the register. When it has time to respond to an interrupt the CPU reads then resets the interrupt counter and reads the interrupt status register to determine the current interrupt count and interrupt addres…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.