Synchronous interface for transmitting data in a system of massively parallel processors
US6185693A · kind A · utility
10Cited by
11References
3Claims
0Family size
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Key dates
| Filing date | Jun 24, 1996 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Jun 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.