Dynamic clock distribution
US6185694A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/363
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system including a first graphics controller and an expansion slot for coupling a second graphics controller. The first graphics controller generates first graphic symbols based on data stored in the system memory in synchronism with clock signals received from a clock circuit. Similarly, the second graphics controller generates second graphic symbols based on data stored in the system memory in synchronism with clock signals received from the clock circuit. When the second graphics controller is not coupled to the expansion slot, the processor provides a graphics select signal. A clock steering circuit responds to the graphics select signal by applying the clock signals to the first graphics controller, while blocking the clock signals to the expansion slot. In the absence of the graphics select signal, the clock steering circuit applies the clock signals to the expansion slot for application to the second graphics controller, while blocking the clock signals to the first graphics controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.