Method for performing timing analysis of a clock-shaping circuit
US6185723A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1996 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Nov 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A methodology is implemented for accurately and precisely computing the output signal times for clock circuit in a data processing system (600) using transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors. During execution of the Static timing analysis, the predictability of clock signals is recognized and denoted in a timing model (616-622). Furthermore, an actual logical function of the clock circuit is determined during execution of the static timing analysis to provide more precise knowledge of the rise and fall times of the signals provided to the clock circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.