Stacked semiconductor chip package having external terminal pads and stackable chips having a protection layer
US6188129A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1998 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Mar 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06551
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The stackable semiconductor chip includes a semiconductor chip having pads on an upper surface thereof, and an adhesive formed on lateral surfaces of the semiconductor chip. A first insulation layer is formed over the upper surface of the semiconductor chip and the adhesive, and defines a plurality of through holes which expose the pads. Metal lines, formed on the first insulation layer, are connected to a respective one of the pads via a respective one of the through holes. A protective layer is formed on the metal lines and the first insulation layer. A plurality of stackable semiconductor chips are stacked by disposing double-sided adhesive between the stackable semiconductor chips. Then a plurality of external terminal pads are formed on one of the lateral surfaces of the stack of stackable semiconductor chips. Each external terminal pad is electrically connected to at least one of the metal lines in one of the stackable semiconductor chips. Next, a solder ball is formed on each of the plurality of external terminal pads to produce a stacked semiconductor chip package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.