Configurable clock generator
US6188255A · kind A · utility
21Cited by
41References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1998 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Sep 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0898
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method implement a configurable clock generator comprising a logic circuit, a configurable matrix and a phase-locked loop. The logic circuit may be configured to generate a plurality of control signals. The configurable matrix may comprise a plurality of interconnections that may be configured to (i) receive the plurality of control signals from the logic circuit and (ii) bus the control signals to the phase-locked loop. The plurality of control signals may control the operation of the phase-locked loop. In one example, the logic circuit may comprise a sea of gates logic array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.