Clock generating circuitry
US6188258A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Apr 5, 1999 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Apr 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Clock generating circuitry comprises a first frequency multiplier for multiplying the frequency of a reference clock applied thereto by 2n, where n is a natural integer, and for furnishing the frequency-multiplied clock, a frequency divider for dividing the frequency of the frequency-multiplied clock furnished by the first frequency multiplier by 227, and for furnishing the frequency-divided clock, and a second frequency multiplier for multiplying the frequency of the frequency-divided clock from the frequency divider by 128, and for furnishing the frequency-multiplied clock. The reference clock can have a frequency of about 4.43 MHz.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.