Low power, static content addressable memory
US6188629A · kind A · utility
23Cited by
5References
11Claims
0Family size
Inventor
Key dates
| Filing date | Nov 5, 1999 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Nov 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low power, static content addressable memory having combinatorial logic gates to connect the selection lines of a plurality of memory cells in a manner that does not compromise the stability of the cells. In one embodiment, each memory cell has one set of complementary bit lines, while in a second embodiment, each memory cell has two or more sets of bit lines to allow simultaneous read operations or simultaneous read and write operations. Because precharging of the selection line is not required, the memory consumes less power in operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.