Synchronous semiconductor memory device having input circuit with reduced power consumption
US6188641A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2000 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Mar 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To reduce wasteful power consumption at an input circuit without increasing in number of exterior wiring, there are provided command input circuits 24 and 26 for latching a command CMD on the rise of an internal clock CLK1, a command decoder for decoding the latched command, a chip select signal input circuits 41, 40 and 20 for activating an enable signal EN1 in response to activation of a chip select signal *CS, deactivating the EN1 in response to deactivation of the *CS after the next pulse of an external clock CLK and generating an internal chip select signal *CSC by synchronizing the *CS with the CLK, a clock input circuit 21 for passing through the CLK while the EN1 is active, and a D-flip-flop for generating a command data activating signal by synchronizing the internal chip select signal *CSC with the CLK1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.