Synchronous digital transmission system

US6188685A · kind A · utility

Assignee

• ALCATEL · FR

Inventors

• Michael Wolf · Mundelsheim, DE
• Geoffrey Dive · Aspach, DE
• Jürgen Kasper · Stuttgart, DE

Key dates

• Filing date: Dec 3, 1996
• Grant date: Feb 13, 2001
• Expiry date: Dec 3, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04J3/0623
• WIPO field: Telecommunications
• WIPO sector: Electrical engineering

Abstract

A transmission system is indicated for digital signals combined into a multiplex signal, and a network element for such a transmission system. Each network element contains an adapter circuit to balance phase variations in an incoming multiplex signal. The adapter circuit has a buffer memory (1) for payload data bytes, a write address generator (2) which controls the buffer memory (1) in a way so that a number of payload data bytes is stored within one write cycle, and has a read address generator (3) which controls the buffer memory (1) in a way so that the number of payload data bytes stored within the write cycle is greater than the number of payload data bytes read during the read cycle. Each network element has a sort facility (5) which sorts the read payload data bytes, so that a multiplex signal that is transmitted by a network element has the established frame format.