Performance monitoring of cache misses and instructions completed for instruction parallelism analysis
US6189072A · kind A · utility
44Cited by
11References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 17, 1996 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Dec 17, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.