Error handling between a processor and a system managed by the processor
US6189117A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1998 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Aug 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0796
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.