Coupling noise reduction technique using reset timing
US6189133A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 14, 1998 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | May 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
False transitions resulting from capacitive coupling between parallel interconnects driven by dynamic circuits are reduced by classifying interconnects based on the timing of expected data transitions in the signals they carry. Interconnects carrying signals expected to transition during a first portion of a processor cycle are treated as one category, while interconnects carrying signals expected to transition during a second, different portion of the processors cycle are treated as a second category. Interconnects of different categories are interdigitated, a resets of dynamic driving circuits are tuned so that, at any given time, alternate interconnects are "quiet" or stable. Therefore interconnects being driven with data transitions are directly adjacent to quiet lines, and foot devices are implemented as necessary to prevent coupling expected during the reset phase. Such foot devices are implemented within receiving circuits to preclude capacitive coupling between the driven interconnect and the quiet line from having any significant effect. Extra quiet lines may be employed as needed. The evaluation phases of dynamic circuits driving adjacent interconnects may overlap, so tha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.