Process for fabricating two different types of wafers in a semiconductor wafer production line
US6190424A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 1995 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Jan 11, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A semiconductor integrated circuit device fabrication method has a main processing line and a sub-processing line. The main processing line includes a plurality of main batch processing sections, each of which processes a plurality of main objects at a time, and a plurality of main sequential processing sections, each of which processes a minimum number of main objects at a time. The main processing line feeds the main objects to the main batch processing sections and the main sequential processing sections for predetermined processing. The sub-processing line includes a plurality of sub-processing sections, each of which performs processing identical with that of a corresponding main batch processing section on a minimum number of sub-objects and certain of the main sequential processing sections. The sub-processing line feeds the sub-objects to the sub-processing sections and the main sequential processing sections for predetermined processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.