Shallow trench isolation method
US6191001A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Aug 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device using shallow trench isolation is provided, wherein a plurality of protrusions are formed in the exposed surface of the mask layer overlying the active area of the device. The protrusions are preferably formed by forming a photo-resist layer on the surface of the mask layer and patterning the photo-resist layer such that the photo-resist layer defines a plurality of protrusion areas and a depression area within the defined active area. A portion of the mask layer is removed in the defined depression area to form a plurality of protrusions in the mask layer. Thereafter, a dielectric layer is deposited on the exposed surface of the mask layer and in the shallow trench and evenly planarized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.