Micromechanical layer stack arrangement particularly for flip chip or similar connections

US6191489A · kind A · utility

Assignee

• Micronas GmbH · DE

Inventors

• Gunter Igel · Teningen, DE
• Hans-Jurgen Gahle · Emmendingen, DE
• Mirko Lehmann · Glückstadt, DE

Key dates

• Filing date: Feb 18, 2000
• Grant date: Feb 20, 2001
• Expiry date: Feb 18, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/351
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process is provided for manufacturing a layer arrangement (1) having a bump for a flip chip or similar connection. The layer arrangement has a plurality of layers (2, 3, 4, 5, 6, 7, 11) made of solid material and stacked into a layer stack (8). A recess (10) that extends over several layers (2, 3, 4, 5, 6, 7, 11) is made in the layer stack (8) transverse to the coating planes of the layers (2, 3, 4, 5, 6, 7, 11). A bump material (14) is placed in the recess (10). A profiling is created on the lateral boundary wall of the recess (10) by removal of layer material of different layers (2, 3, 4, 5, 6, 7, 11) of the layer stack (8). The profiling, starting from the surface (9) of the layer stack (8) and progressing in layers to the inside of the recess (10), has at least two indentations (12) and at least one projection (13) located between them. After the production of the profiling, a bump material (14) is brought into the recess (10) in such a way that it grasps behind the indentations (12).