Logic circuit having reduced power consumption
US6191615A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Mar 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic circuit which is driven at low voltage and operates at high speed and low power consumption is provided. Substrate potentials of P and N type transistors MP11 and MN11 constituting an inverter are controlled correspondingly to a stable state of the inverter. In a stable state of the inverter in which the P type transistor MP11 is ON, the substrate potential of the N type transistor MN11 which is OFF is lowered to ground potential or lower and, in a stable state of the inverter in which the N type transistor MN11 is ON, the substrate potential of the P type transistor MP11 which is OFF is raised to a power source potential or higher.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.