Frequency synthesizer with a phase-locked loop with multiple fractional division
US6191657A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1991 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Jul 2, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesizer comprises a single phase-locked loop controlled by a reference clock formed by a voltage-controlled oscillator, a programmable divider with variable division rank M, a phase detector, and a loop filter. It also comprises a predetermined number n of fractional division structures, each implementing a frequency step P.sub.i.times.F.sub.reF lower than the reference frequency F.sub.ref. Each fractional structure is coupled in parallel with said programmable divider to add to said division rank M fractional increments P.sub.i such that the ratio between the frequency F.sub.vco provided by said oscillator and said reference frequency be defined as a function of said increments P.sub.i by the relationship: ##EQU1##
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.