Non-volatile NAND type semiconductor memory device with stacked gate memory cells and a stacked gate select transistor
US6191975A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Dec 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the field of EEPROM, memory cell structures and operation methods have been required which are suitable for ultrahigh-integration and high-reliability EEPROMS with no danger of erroneous writing. To meet this requirement, in this invention, the gate of each of select gate cells located on the source line side and the bit line side of a NAND type memory cell array is formed of two layers of a charge storage layer and a control gate layer as with memory cells. The select gate cells are formed at the same time in the same process as memory cells. The ion implantation conditions for the cell channels are set so as to optimize the memory cell channel boost ratio. The optimization of the cutoff characteristic required of the select gate cells is performed by injection of charges into the charge storage layers of the select gate cells without owing to ion implantation. The memory and select gate cells are formed into the same shape. The charge storage layer is formed to self-align to an isolation trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.