Sense circuit for a multi-level flash memory cell
US6191977A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Mar 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense circuit for multi-level flash memory cell includes a control signal generator for generating a plurality of voltage control signals, a clock signal having constant period and a plurality of control pulses according to a sense amplifier enable signal; a control voltage generator for generating multi-steps voltage according to the clock signal and the plurality of voltage control signals, sequentially supplying the multi-steps voltage to a program gate of the memory cell, generating a reference voltage according to the sense amplifier enable signal and supplying the reference voltage to a program gate of a reference cell; and a sense amplifier for sequentially comparing a plurality of data stored in the memory cell and a data of the reference cell, storing the result according to the control pulse and converting it into binary data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.